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Designing an Efficient Process using IDesignSpec

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IDesignSpec not only enables you to create consistent, high quality hardware specifications but also quickly and efficiently generate code from it. It is an easy to use Plugin for all popular Editors- MS Word, MS Excel, and FrameMaker®, that allows automatic code generation for UVM, OVM, VMM, RTL, C/C++ headers and many more outputs.
Following paragraphs detail how IDesignSpec provides unique value to the Chip design and development process.
SoC chip level specification
IDesignSpec enables the design abstraction from IP level to SoC Level. In IDesignSpec, user can easily specify the register definition that spans from a single IP block containing few hundreds of registers to a chip or even SoC containing thousands of register. All the documentation, Design RTLs, Verification HVLs like UVM/OVM/VMM/eRM and Firmware Codes like C/C++ can be generated by just a single click.
Parallel development
IDesignSpec allows the SoC designer to start designing while the IPs are still under development by “referring” to them. This ensures that any changes made in IP will be available in the SoC automatically. Also referring the various legacy IPs promote the reuse by not having to re-specify the IPs into the new design.
Multiple variants of same document source
Same Register Specification document can be used to generate the various different outputs conditionally depending upon the selected variant. The variants can be combined to form a complex Boolean expression and these expressions can be used to specify a condition under which a particular element will be included or excluded from the register model.
Increase the work speed
User can easily integrate IDesignSpec into his existing simulation environment using the Batch mode operation. Users register specification available in Word, Excel, OpenOffice or CSV format can be used as input source for IDesignSpec in Batch mode (IDSBatch) to generate the various outputs. Also user can read-in the register specifications available in the industry standard formats such as IP-XACT or SystemRDL directly into IDSBatch  to generate various outputs.
Create spec document from industry standards
Various Industry Standards such as IP-XACT and SystemRDL can be read into IDesignSpec to create visually more appealing specification and use this specification to generate the various outputs as required by the user.
Single source documentation for design, verification and firmware
IDesignSpec enables users to use the single source to generate all the possible codes such as design RTLs, Verification HVLs and Firmware codes and documentation and industry standards such as IP-XACT, SystemRDL, HTML and PDF. Using the single source ensures consistency, any change in the specification leads to changes for all outputs. Thus by using IDesignSpec, User can make the required changes in the register specification and with a single click of button everything can be regenerated in no time.
Parametrization in document
Like any other language, IDesignSpec takes forward the trend of Parametrization from codes right into specification.
PDF generation – command line interactive
Various deliverable documentation formats such as PDF and HTML can be generated from various industry standards or user documentation in interactive mode using Excel/Word/OpenOffice or in command-line mode using IDSBatch. PDF generation – Command line or interactive
IDesignSpec has the ability to scale for the large projects. Our design and verification tools have boosted productivity of our customers by eliminating volumes of manual work. Its specialized plugins enables designers to create correct-by-construction, reusable designs.
For any further queries please contact Agnisys Customer Care Team at [email protected] We will provide installation and maintenance of the IDesignSpec with latest features while the tool will itself provide its benefits as you explore it further.
About The Author:
Agnisys offers innovative verification management tools that make design verification process extremely efficient and high quality. Agnisys offer free UVM register generator. Also provide high quality IP XACT specifications for documenting IP’s. Get value of high quality IP XACT XML. Agnisys generate automatic MS Word documentation for your entire SystemRDL files.


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  • Posted On June 1, 2012
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